`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:58:54 09/08/2012
// Design Name:   dis_peatonal
// Module Name:   C:/Users/maye/Desktop/taller/lab2/lab2/dis_pea_pru.v
// Project Name:  lab2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: dis_peatonal
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module dis_pea_pru;

	// Inputs
	reg rst_i;
	reg [3:0] value_i;
	reg peatonal_i;
	reg clk_i;

	// Outputs
	wire [3:0] segmentos_o;

	// Instantiate the Unit Under Test (UUT)
	dis_peatonal uut (
		.rst_i(rst_i), 
		.value_i(value_i), 
		.peatonal_i(peatonal_i), 
		.clk_i(clk_i), 
		.segmentos_o(segmentos_o)
	);
	
	always begin 
		#50 clk_i=~clk_i;
	end	

	initial begin
		// Initialize Inputs
		rst_i = 0;
		value_i = 6;
		peatonal_i = 0;
		clk_i = 0;

		// Wait 100 ns for global reset to finish
		#1000;
		peatonal_i=1;
		#100;
		peatonal_i=0;
		// Add stimulus here

	end
      
endmodule

